Method for fabricating semiconductor device using a cvd insulator film

ABSTRACT

A gate insulator film and a gate electrode are formed on an Si substrate, and a CVD insulator film is deposited thereon to cover the gate electrode. Then, arsenic ions are implanted into the Si substrate from above the CVD insulator film to form LDD layers. After sidewall spacers have been formed over the side faces of the gate electrode with the CVD insulator film interposed therebetween, source/drain layers are formed. Since the LDD layers are formed by implanting dopant ions through the CVD insulator film, the passage of arsenic ions through the ends of the gate electrode can be suppressed. As a result, a semiconductor device suitable for miniaturization can be formed, while suppressing deterioration in insulating properties of the gate oxide film due to the passage of dopant ions through the ends of the gate electrode.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to a method for fabricating asemiconductor device including a highly reliable gate insulator film andfunctioning as an MOS field effect transistor (MOSFET) or a nonvolatilesemiconductor memory device.

[0002] In a great number of fields, semiconductor devices such asMOSFET's or nonvolatile semiconductor memory devices have been used verywidely and frequently. As is well known in the art, in a MOSFET, a gateelectrode is formed on a gate insulator film, an underlying region ofwhich functions as channel region. Source/drain layers are formed onboth sides of the channel. And the value of current flowing between thesource/drain layers and the ON/OFF states of the device are controlledbased on a voltage applied to the gate electrode. A nonvolatilesemiconductor memory device includes not only the members of a MOSFETbut also a floating gate electrode, interposed between the gateinsulator film and the gate electrode of a MOSFET, for retainingcharges.

[0003] FIGS. 15(a) through 15(d) are cross-sectional views illustratingrespective process steps for fabricating a prior art semiconductordevice functioning as a MOSFET. As shown in FIG. 15(d), the deviceincludes: a semiconductor substrate 111; a gate oxide film 112; a gateelectrode 113; LDD layers 115 a and 115 b; sidewall spacers 116 a and116 b; and source/drain layers 117 and 118. In FIG. 15(b), the referencenumeral 114 denotes arsenic ions implanted as dopant ions into thesubstrate 111 to form the LDD layers 115 a and 115 b.

[0004] Hereinafter, a method for fabricating the prior art semiconductordevice will be described with reference to FIGS. 15(a) through 15(d).

[0005] First, in the process step shown in FIG. 15(a), a gate electrode113 is formed over an Si substrate 111 of a first conductivity type(e.g., P-type) with a gate oxide film 112 interposed therebetween.

[0006] Next, in the process step shown in FIG. 15(b), arsenic ions 114are implanted as low-concentration dopant ions of a second conductivitytype from above the gate electrode 113 into the Si substrate 111. As aresult, LDD layers 115 a and 115 b are formed inside the Si substrate111 on both sides of the gate electrode 113.

[0007] Then, in the process step shown in FIG. 15(c), an insulator filmsuch as a silicon dioxide film is deposited over the substrate, and thenetched anisotropically to form sidewall spacers 116 a and 116 b on theside faces of the gate electrode 113. In this process step, portions ofthe gate oxide film 112, not covered with the gate electrode 113 or thesidewall spacers 116 a and 116 b, are also etched.

[0008] Thereafter, in the process step shown in FIG. 15(d), arsenic ionsare implanted as high-concentration dopant ions of the secondconductivity type from above the gate electrode 113 and the sidewallspacers 116 a and 116 b into the Si substrate 111. As a result,source/drain layers 117 and 118 are formed along the outer periphery ofthe LDD layers 115 a and 115 b, respectively.

[0009] A nonvolatile semiconductor memory device having a structure inwhich gate oxide film, floating gate electrode, ONO film and controlgate electrode are stacked one upon the other is also formed basicallyby performing the same steps as those shown in FIGS. 15(a) through15(d).

[0010] A conventional MOSFET or nonvolatile semiconductor memory devicehaving such a structure has problems that the leakage or disturbcharacteristics (variation in threshold voltage with time) thereof aregreatly variable or deteriorative and that the values themselves shouldalso be improved to a large degree. In order to spot the root of theseproblems, the present inventors carried out intensive research on whatbrings about such variation or deterioration in characteristics. As aresult, we arrived at a conclusion that such variation or deteriorationmight possibly result from the damage caused at the ends of a gate oxidefilm during the implantation of dopant ions. Specifically, in theprocess step of implanting dopant ions as shown in FIG. 15(b), the ionsare usually implanted obliquely, e.g., at a tilt angle of about 7degrees with respect to a normal of the substrate surface to preventchanneling. Accordingly, during this process step, the dopant ions mightpass through the ends of the gate oxide film to be unintentionallyintroduced into the gate oxide film. Similarly, in a nonvolatilesemiconductor memory device, dopants seem to be accidentally introducedinto an interlevel dielectric film made of ONO, for example, as well asinto the gate oxide film.

[0011] Also, it was already observed that unwanted bird's beaks areformed at locally thickened ends of a gate oxide film during afabrication process including a processing step of conducting a heattreatment in an oxidizing ambient. If such bird's beaks are formed, thenthe gate length has virtually increased. Thus, the same effects as thosecaused with an increased gate length are possibly brought about. That isto say, the threshold voltage might become variable.

[0012] In a nonvolatile semiconductor memory device, in particular, ifbird's beaks are formed in a gate oxide film, then the efficiency, withwhich electrons are injected/ejected into/out of the gate, adverselydeteriorates. Also, if bird's beaks are formed in an interleveldielectric film between floating gate and control gate electrodes, thenstress might be locally applied to these beaks, resulting indeterioration in characteristics of the device.

SUMMARY OF THE INVENTION

[0013] An object of this invention is providing a method for fabricatinga semiconductor device functioning as a MOSFET with characteristics suchas threshold voltage less variable or improved by taking variousmeasures to prevent damage or bird's beaks from being caused at bothends of a gate oxide film.

[0014] Another object of the present invention is providing a method forfabricating a semiconductor device functioning as a nonvolatilesemiconductor memory device with characteristics such as thresholdvoltage less variable or improved by taking various measures to preventdamage or bird's beaks from being caused in a gate oxide film.

[0015] A first method according to the present invention is a method forfabricating a semiconductor device functioning as an MOS field effecttransistor. The method includes the steps of: a) forming a gateinsulator film and a gate electrode on a semiconductor substrate in thisorder; b) forming a CVD insulator film to cover an exposed surface ofthe gate electrode by performing a CVD process; c) forming LDD layers inthe semiconductor substrate by implanting dopant ions into thesemiconductor substrate from above the gate electrode and the CVDinsulator film; d) forming sidewall spacers over the side faces of thegate electrode with the CVD insulator film interposed therebetween; ande) forming source/drain layers in the semiconductor substrate.

[0016] In accordance with this method, it is possible to suppress thepassage of dopant ions, implanted into the semiconductor substrate inthe step c), through the ends of the gate electrode, resulting in thesuppression of damage caused in the gate insulator film. Accordingly, asemiconductor device including a highly reliable gate insulator film canbe fabricated and the reliability of the semiconductor device can beimproved. In addition, since an insulator film can be grown by CVD at atemperature as low as 800° C. or less, no bird's beaks are formed in thegate insulator film. Thus, the CVD insulator film constitutes noobstacle to the miniaturization of a semiconductor device. Furthermore,since the gate electrode is covered with the CVD insulator film, it ispossible to prevent the dopants introduced into the gate electrode fromdiffusing to pass through the gate electrode. As a result, asemiconductor device with less variable characteristics can be formed.

[0017] In one embodiment of the present invention, the first method mayfurther include, between the steps b) and c), the step of etchinganisotropically the CVD insulator film to leave the CVD insulator filmat least on the side faces of the gate electrode.

[0018] In such an embodiment, portion of the CVD insulator film on thesemiconductor substrate can be removed and thus the implant energy ofthe dopant ions can be reduced during the formation of the LDD layers.Accordingly, it is possible to suppress the passage of the dopant ionsthrough both ends of the gate electrode with much more certainty.

[0019] It should be noted that if the steps of forming the CVD insulatorfilm and implanting the dopant ions are performed two or more, an LDDstructure having a gentler dopant concentration profile can be obtainedand a semiconductor device with excellent electrical characteristics canbe obtained.

[0020] In another embodiment of the present invention, the thickness ofthe CVD insulator film is preferably in the range from 5 nm to 30 nm.

[0021] In such an embodiment, it is possible to reduce the damage causedin the gate insulator film due to the ion implantation with morecertainty. In addition, the LDD layers and the gate electrode canoverlap with each other by an appropriate distance without conducting anexcessive heat treatment.

[0022] In another embodiment of the present invention, the first methodmay further include, posterior to the step c), the step of conducting aheat treatment within an ambient containing at least oxygen to repairdamage caused in the gate insulator film due to the implantation of thedopant ions.

[0023] In such an embodiment, the leakage resulting from the existenceof damage can be reduced more effectively and unwanted phenomena such asvariation in threshold voltage with time can be suppressed.

[0024] In still another embodiment, the step of conducting a heattreatment is preferably performed within an oxidizing and nitridingambient.

[0025] In such an embodiment, carrier trapping can also be reduced,because dangling bonds existing between the gate insulator film and thesemiconductor substrate can be repaired.

[0026] A second method according to the present invention is a methodfor fabricating a semiconductor device functioning as an MOS fieldeffect transistor. The method includes the steps of: a) forming a gateinsulator film and a gate electrode on a semiconductor substrate in thisorder; b) forming an insulating coating to cover an exposed surface ofthe gate electrode; c) forming LDD layers in the semiconductor substrateby implanting dopant ions into the semiconductor substrate from abovethe gate electrode and the insulating coating; d) conducting a heattreatment within an ambient containing at least oxygen to repair damagecaused in the gate insulator film due to the implantation of the dopantions; e) forming sidewall spacers over the side faces of the gateelectrode with the insulating coating interposed therebetween; and f)forming source/drain layers in the semiconductor substrate.

[0027] In accordance with this method, the leakage resulting from theexistence of damage in the gate insulator film can be reduced moreeffectively and unwanted phenomena such as variation in thresholdvoltage with time can be suppressed.

[0028] In one embodiment of the present invention, the step d) ispreferably performed within an oxidizing and nitriding ambient.

[0029] In such an embodiment, carrier trapping can also be reduced,because dangling bonds can be repaired.

[0030] In another embodiment of the present invention, the heattreatment is preferably conducted in the step d) as rapid thermalannealing at a temperature in the range from 800° C. to 1100° C. within120 seconds.

[0031] In such an embodiment, it is possible to suppress variation indevice characteristics due to the bird's beaks formed in the gateinsulator film.

[0032] A third method according to the present invention is a method forfabricating a semiconductor device functioning as a nonvolatilesemiconductor memory device. The method includes the steps of: a)forming a gate insulator film, a floating gate electrode, an interleveldielectric film and a control gate electrode on a semiconductorsubstrate in this order; b) forming a CVD insulator film to cover thesurfaces of the floating gate electrode, the interlevel dielectric filmand the control gate electrode by performing a CVD process; and c)forming source/drain layers in the semiconductor substrate by implantingdopant ions into the semiconductor substrate from above the CVDinsulator film, the control gate electrode, the interlevel dielectricfilm and the floating gate electrode.

[0033] In accordance with this method, it is possible to suppress thepassage of the dopant ions, implanted into the semiconductor substratein the step c), through the ends of the floating gate electrode,resulting in the suppression of damage caused at the ends of the gateinsulator film. Accordingly, a nonvolatile semiconductor memory deviceincluding a highly insulating and reliable gate insulator film can befabricated. As a result, rewriting can be performed in the nonvolatilesemiconductor memory device a considerably larger number of times andvarious disturb characteristics can be improved. In addition, since aninsulator film can be grown by CVD at a temperature as low as 800° C. orless, no bird's beaks are formed in the gate insulator film. Thus, theCVD insulator film constitutes no obstacle to the miniaturization of asemiconductor device. Furthermore, since the side faces of the floatinggate electrode are covered with the CVD insulator film, it is possibleto prevent the dopants introduced into the floating gate electrode fromdiffusing to pass through the gate electrode. As a result, a nonvolatilesemiconductor memory device exhibiting less variable characteristics andexcelling in charge retention time can be fabricated.

[0034] In one embodiment of the present invention, the third method mayfurther include, between the steps b) and c), the step of etchinganisotropically the CVD insulator film to leave the CVD insulator filmat least on the side faces of the floating gate electrode.

[0035] In another embodiment, the thickness of the CVD insulator film ispreferably in the range from 5 nm to 30 nm.

[0036] In still another embodiment, the third method may furtherinclude, posterior to the step c), the step of conducting a heattreatment within an ambient containing at least oxygen to repair damagecaused in the gate insulator film due to the implantation of the dopantions.

[0037] In such an embodiment, the variation in threshold voltage withtime can be reduced and rewriting can be performed an even larger numberof times.

[0038] In still another embodiment, the step of conducting a heattreatment may be performed within an oxidizing and nitriding ambient.

[0039] In such an embodiment, carrier trapping can also be reduced,because dangling bonds existing between the gate insulator film and thesemiconductor substrate can be repaired.

[0040] A fourth method according to the present invention is a methodfor fabricating a semiconductor device functioning as a nonvolatilesemiconductor memory device. The method includes the steps of: a)forming a gate insulator film, a floating gate electrode, an interleveldielectric film and a control gate electrode on a semiconductorsubstrate in this order; b) forming an insulating coating to cover thesurfaces of the floating gate electrode, the interlevel dielectric filmand the control gate electrode; c) forming source/drain layers in thesemiconductor substrate by implanting dopant ions into the semiconductorsubstrate from above the insulating coating, the control gate electrode,the interlevel dielectric film and the floating gate electrode; and d)conducting a heat treatment within an ambient containing at least oxygento repair damage caused in the gate insulator film due to theimplantation of the dopant ions.

[0041] In accordance with this method, the leakage characteristicsresulting from the damage in the gate insulator film can be improved.Accordingly, variation in threshold voltage with time can be reduced andrewriting can be performed a far larger number of times.

[0042] In one embodiment of the present invention, the step d) may beperformed within an oxidizing and nitriding ambient.

[0043] In such an embodiment, carrier trapping can also be reduced,because dangling bonds existing between the gate insulator film and thesemiconductor substrate can be repaired.

[0044] In another embodiment of the present invention, the heattreatment is preferably conducted in the step d) as rapid thermalannealing at a temperature in the range from 800° C. to 1100° C. within120 seconds.

BRIEF DESCRIPTION OF THE DRAWINGS

[0045] FIGS. 1(a) through 1(e) are cross-sectional views illustratingrespective process steps for fabricating a semiconductor devicefunctioning as a MOSFET according to the first embodiment of the presentinvention.

[0046] FIGS. 2(a) through 2(e) are cross-sectional views illustratingrespective process steps for fabricating a semiconductor devicefunctioning as a MOSFET according to the second embodiment of thepresent invention.

[0047]FIG. 3 is a graph illustrating how leakage current flowing througha gate oxide film varies with the thickness of a CVD insulator film(silicon dioxide film) in respective embodiments of the presentinvention.

[0048] FIGS. 4(a) through 4(c) are cross-sectional views illustratingrespective process steps for fabricating a semiconductor devicefunctioning as a nonvolatile semiconductor memory device according tothe third embodiment of the present invention.

[0049] FIGS. 5(a) through 5(c) are cross-sectional views illustratingrespective process steps for fabricating a semiconductor devicefunctioning as a nonvolatile semiconductor memory device according tothe fourth embodiment of the present invention.

[0050]FIG. 6 is a cross-sectional view of a semiconductor devicefunctioning as a MOSFET according to the fifth embodiment of the presentinvention.

[0051]FIG. 7 is a cross-sectional view of a semiconductor devicefunctioning as a nonvolatile semiconductor memory device according tothe sixth embodiment of the present invention.

[0052] FIGS. 8(a) through 8(f) are cross-sectional views illustratingrespective process steps for fabricating a semiconductor devicefunctioning as a MOSFET according to the seventh embodiment of thepresent invention.

[0053] FIGS. 9(a) through 9(f) are cross-sectional views illustratingrespective process steps for fabricating a semiconductor devicefunctioning as a MOSFET according to the eighth embodiment of thepresent invention.

[0054] FIGS. 10(a) through 10(f) are cross-sectional views illustratingrespective process steps for fabricating a semiconductor devicefunctioning as a MOSFET according to the ninth embodiment of the presentinvention.

[0055] FIGS. 11(a) through 11(d) are cross-sectional views illustratingrespective process steps for fabricating a semiconductor devicefunctioning as a nonvolatile semiconductor memory device according tothe tenth embodiment of the present invention.

[0056] FIGS. 12(a) through 12(d) are cross-sectional views illustratingrespective process steps for fabricating a semiconductor devicefunctioning as a nonvolatile semiconductor memory device according tothe eleventh embodiment of the present invention.

[0057] FIGS. 13(a) through 13(d) are cross-sectional views illustratingrespective process steps for fabricating a semiconductor devicefunctioning as a nonvolatile semiconductor memory device according tothe twelfth embodiment of the present invention.

[0058]FIG. 14 is a graph illustrating in comparison data about themaximum numbers of times rewriting can be performed in respectivenonvolatile semiconductor memory devices fabricated by the methods ofthe third and tenth embodiments.

[0059] FIGS. 15(a) through 15(d) are cross-sectional views illustratingrespective process steps for fabricating a semiconductor devicefunctioning as a MOSFET in the prior art.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0060] Embodiment 1

[0061] Hereinafter, the first embodiment of the present invention willbe described. FIGS. 1(a) through 1(e) are cross-sectional viewsillustrating respective process steps for fabricating a semiconductordevice functioning as a MOSFET according this embodiment.

[0062] As shown in FIG. 1(e), the device includes: an Si substrate 11; agate oxide film 12; a gate electrode 13; LDD layers 15 a and 15 b;sidewall spacers 16 a and 16 b; source/drain layers 17 and 18; and a CVDinsulator film 19. The CVD insulator film 19 is made of silicon dioxidedeposited by a CVD process. In FIG. 1(c), the reference numeral 14denotes arsenic ions implanted as dopant ions into the Si substrate 11to form the LDD layers 15 a and 15 b.

[0063] First, in the process step shown in FIG. 1(a), a gate oxide film12, made of silicon dioxide, is formed by pyrogenic oxidation techniqueto be 9 nm thick on the P-type silicon substrate 11. And then, a gateelectrode 13 made of phosphorus-doped polysilicon is formed thereon.

[0064] Next, in the process step shown in FIG. 1(b), a CVD insulatorfilm 19, made of silicon dioxide, is deposited by reduced pressure CVD(RPCVD) to be 10 nm thick over the substrate to cover the gate oxidefilm 12 and the gate electrode 13.

[0065] Then, in the process step shown in FIG. 1(c), arsenic ions 14 areimplanted into the Si substrate 11 from above the gate electrode 13 andthe CVD insulator film 19 to form N-type LDD layers 15 a and 15 b in theSi substrate 11 on both sides of the gate electrode 13. The implantationis performed under the conditions that the implant energy is 50 keV andthe dose is 5×10¹⁴ cm⁻², for example. Also, in order to make the LDDlayers 15 a and 15 b extend to reach a region near the gate electrode13, the ions are implanted at a tilt angle of about 25 degrees withrespect to a normal of the substrate (where implantation is performed atfour steps).

[0066] Subsequently, in the process step shown in FIG. 1(d), a TEOS filmis deposited over the substrate and etched anisotropically to formsidewall spacers 16 a and 16 b over the side faces of the gate electrode13 with the CVD insulator film 19 interposed therebetween. During thisprocess step, portions of the gate oxide film 12 and the CVD insulatorfilm 19 on the Si substrate 11 are removed.

[0067] Finally, in the process step shown in FIG. 1(e), arsenic ions areimplanted into the Si substrate 11 from above the gate electrode 13, theCVD insulator film 19 and the sidewall spacers 16 a and 16 b. As aresult, N-type source/drain layers 17 and 18 are formed in the Sisubstrate 11 along the outer periphery of the LDD layers 15 a and 15 b.The implantation is performed under the conditions that the implantenergy is 50 keV and the dose is 2×10¹⁵ cm⁻², for example. Also, inorder to prevent channeling, the ions are implanted at a tilt angle ofabout 7 degrees with respect to a normal of the substrate.

[0068] In accordance with the method of this embodiment, the side facesof the gate electrode 13 are covered with the CVD insulator film 19 inthe process step shown in FIG. 1(c). Accordingly, it is possible tosuppress the passage and introduction of the arsenic ions 14, implantedinto the Si substrate 11 to form the LDD layers 15 a and 15 b, throughthe ends of the gate electrode 13 into the gate oxide film 12 under theelectrode 13. Thus, the damage caused in the gate oxide film 12,specifically, portion of the gate oxide film 12 actually functioning asa gate insulator film under the gate electrode 13, by the conventionalmethod can be suppressed. As a result, a semiconductor device includinga highly insulating and reliable gate oxide film can be obtained. Inother words, the reliability of a semiconductor device functioning as aMOSFET can be improved. It should be noted that in this specification,the “damage in the gate oxide film” means the damage caused in theportion of the film actually functioning as a gate insulator film underthe gate electrode.

[0069] In addition, the CVD insulator film 19 is grown by a CVD processat a temperature as low as about 800° C. or less. Accordingly, unlikeforming a thick protective oxide film by conducting thermal oxidation ata relatively high temperature, no bird's beaks are formed at both endsof the portion of the gate oxide film 12 under the gate electrode 13,i.e., the portion actually functioning as a gate insulator film. Thus,the gate length can be controlled accurately and this method isadvantageously applicable to the miniaturization of a semiconductordevice. Also, since a CVD process is conducted at a lower temperaturethan a thermal oxidation process, it is possible to suppress thediffusion of the dopants such as phosphorus introduced into the gateelectrode 13 toward the gate oxide film 12 under the electrode 13 or theSi substrate 11.

[0070] Furthermore, by covering the gate electrode 13 with the CVDinsulator film 19, it is also possible to prevent the dopants in thegate electrode 13 from diffusing toward the side and upper surfacesthereof. As a result, a semiconductor device with less variablecharacteristics can be advantageously obtained.

[0071] It is noted that before or after the step of implanting arsenicions 14 as shown in FIG. 1(c), B (boron) or BF₂ ions may be implantedinto the Si substrate 11 from above the CVD insulator film 19 and thegate oxide film 12 to form a P-type layer as a punch through stopper.Also, P (phosphorus) ions may be implanted instead of arsenic ions. Itis clear that the same effects as those of this embodiment can beattained even in these cases.

[0072] Embodiment 2

[0073] Next, the second embodiment of the present invention will bedescribed. FIGS. 2(a) through 2(e) are cross-sectional viewsillustrating respective process steps for fabricating a semiconductordevice functioning as a MOSFET of this embodiment.

[0074] As shown in FIG. 2(e), the device includes: an Si substrate 11; agate oxide film 12; a gate electrode 13; LDD layers 15 a and 15 b;sidewall spacers 16 a and 16 b; source/drain layers 17 and 18; and a CVDinsulator film 19. The CVD insulator film 19 is made of silicon dioxidedeposited by a CVD process. In FIG. 2(c), the reference numeral 14denotes arsenic ions implanted as dopant ions into the Si substrate 11to form the LDD layers 15 a and 15 b.

[0075] First, in the process step shown in FIG. 2(a), a gate oxide film12, made of silicon dioxide, is formed to be 9 nm thick on a P-typesilicon substrate 11. And then, a gate electrode 13, made ofphosphorus-doped polysilicon, is formed thereon.

[0076] Next, in the process step shown in FIG. 2(b), a CVD insulatorfilm 19, made of silicon dioxide, is deposited by RPCVD to be 10 nmthick over the substrate to cover the gate oxide film 12 and the gateelectrode 13. Then, the CVD insulator film 19 is etched anisotropically,thereby removing the CVD insulator film 19 except for its portions onthe side faces of the gate electrode 13 and the gate oxide film 12except for its portion under the gate electrode 13.

[0077] Then, in the process step shown in FIG. 2(c), arsenic ions 14 areimplanted into the Si substrate 11 from above the gate electrode 13 andthe CVD insulator film 19 to form N-type LDD layers 15 a and 15 b in theSi substrate 11 on both sides of the gate electrode 13. The implantationis performed under the conditions that the implant energy is 30 keV andthe dose is 5×10¹⁴ cm⁻², for example. Also, in order to make the LDDlayers 15 a and 15 b extend to reach a region near the gate electrode13, the ions are implanted at a tilt angle of about 25 degrees withrespect to a normal of the substrate (where implantation is performed atfour steps).

[0078] Subsequently, in the process step shown in FIG. 2(d), a TEOS filmis deposited over the substrate and etched anisotropically to formsidewall spacers 16 a and 16 b out of the TEOS film over the side facesof the gate electrode 13 with the CVD insulator film 19 interposedtherebetween.

[0079] Finally, in the process step shown in FIG. 2(e), arsenic ions areimplanted into the Si substrate 11 from above the gate electrode 13, theCVD insulator film 19 and the sidewall spacers 16 a and 16 b. As aresult, N-type source/drain layers 17 and 18 are formed in the Sisubstrate 11 along the outer periphery of the LDD layers 15 a and 15 b.The implantation is performed under the conditions that the implantenergy is 50 keV and the dose is 2×10¹⁵ cm⁻², for example. Also, inorder to prevent channeling, the ions are implanted at a tilt angle ofabout 7 degrees with respect to a normal of the substrate.

[0080] In accordance with the method of this embodiment, the side facesof the gate electrode 13 are covered with the CVD insulator film 19 inthe process step shown in FIG. 2(c). Accordingly, it is possible tosuppress the passage of the arsenic ions 14, implanted into the Sisubstrate 11 to form the LDD layers 15 a and 15 b, through the ends ofthe gate electrode 13. Thus, the same effects as those of the firstembodiment can also be attained in this embodiment. In the method ofthis embodiment, in particular, the CVD insulator film 19 has beenremoved in the process step shown in FIG. 2(b) except for its portionson the side faces of the gate electrode 13. Accordingly, the implantenergy may be smaller during the implantation of the dopant ions. As aresult, the quantity of dopants passing through the CVD insulator film19 on the side faces of the gate electrode 13 to reach the gate oxidefilm 12 can be advantageously reduced as compared with the fabricationprocess of the first embodiment.

[0081] It should be noted that before or after the step of implantingarsenic ions 14 shown in FIG. 2(c), B (boron) or BF₂ ions may beimplanted into the Si substrate 11 from above the CVD insulator film 19and the gate oxide film 12 to form a P-type layer as a punch throughstopper. It is clear that the same effects as those of this embodimentcan be attained even in such a case.

[0082] Also, if the steps of depositing the CVD insulator film 19 andimplanting dopant ions to form the LDD layers 15 a and 15 b arerepeatedly performed twice or more with a gradually increased dopinglevel, then an LDD structure having a gentler dopant concentrationprofile can be obtained. As a result, a semiconductor device exhibitingexcellent electrical characteristics is realized.

Appropriate Thickness Range of CVD Insulator Film

[0083] Next, an appropriate thickness range of the CVD insulator film 19defined in the first and second embodiments will be described.

[0084]FIG. 3 is a graph illustrating how leakage current flowing throughthe gate oxide film varies with the thickness of the CVD insulator film.In FIG. 3, the axis of abscissas indicates the thickness of the CVDinsulator film, while the axis of ordinates indicates the leakagecurrent flowing through the gate oxide film. As shown in FIG. 3, if thethickness of the CVD insulator film deposited is 5 nm or more, then theleakage current flowing through the gate oxide film drasticallydecreases. Thus, it can be understood that the deposition of the CVDinsulator film greatly contributes to the reduction of the damage causedin the gate oxide film due to the ion implantation. As shown in FIG. 3,the thicker the CVD insulator film is, the more remarkably the damagecan be reduced. However, in order to overlap the LDD layers with thegate electrode by an appropriate distance without conducting excessiveheat treatment, the thickness of the CVD insulator film is preferably 30nm or less.

[0085] In the first and second embodiments, the CVD insulator film 19 ismade of silicon dioxide. Alternatively, the CVD insulator film 19 may bemade of silicon nitride. With the silicon dioxide CVD insulator film 19,stress applied to the underlying film can be smaller than a siliconnitride film. On the other hand, with a silicon nitride CVD insulatorfilm 19, the formation of bird's beaks in the gate oxide film 12 can beadvantageously suppressed more effectively during subsequent processsteps performed at a high temperature like diffusing the dopants. Thesame trade-off rule is also true of the embodiments of a MOSFET to bedescribed below.

[0086] Embodiment 3

[0087] Next, the third embodiment of the present invention will bedescribed. FIGS. 4(a) through 4(c) are cross-sectional viewsillustrating respective process steps for fabricating a semiconductordevice functioning as a nonvolatile semiconductor memory device of thisembodiment.

[0088] As shown in FIG. 4(c), the device includes: an Si substrate 11; agate oxide film 12; source/drain layers 17 and 18; an insulating coating19 deposited by CVD; a floating gate electrode 20; an interleveldielectric film 21; and a control gate electrode 22. In FIG. 4(c), thereference numeral 23 denotes phosphorus ions implanted as dopant ionsinto the Si substrate 11 to form the source/drain layers 17 and 18.

[0089] First, in the process step shown in FIG. 4(a), a gate oxide film12, made of silicon dioxide, is formed to be 9 nm thick on a P-typesilicon substrate 11. Then, a floating gate electrode 20 made ofphosphorus-doped polysilicon, an interlevel dielectric film 21 made ofONO (three-layered film in which a nitride film is sandwiched between apair of oxide films), and a control gate electrode 22 made ofphosphorus-doped polysilicon are sequentially stacked thereon.

[0090] Next, in the process step shown in FIG. 4(b), a CVD insulatorfilm 19, made of silicon dioxide, is deposited by RPCVD to be 10 nmthick over the substrate to cover the gate oxide film 12 and themultilevel structure including the floating gate electrode 20,interlevel dielectric film 21 and control gate electrode 22.

[0091] Subsequently, in the process step shown in FIG. 4(c), phosphorusions 23 are implanted into the Si substrate 11 from above the controlgate electrode 22, the interlevel dielectric film 21 and floating gateelectrode 20 covered with the CVD insulator film 19. As a result, N-typesource/drain layers 17 and 18 are formed in the Si substrate 11 on bothsides of the floating gate electrode 20. The implantation is performedunder the conditions that the implant energy is 70 keV and the dose is5×10¹⁵ cm⁻², for example. Also, in order to prevent channeling, the ionsare implanted at a tilt angle of about 7 degrees with respect to anormal of the substrate surface.

[0092] In accordance with the method of this embodiment, the side facesof the floating gate electrode 20 are covered with the CVD insulatorfilm 19 in the process step shown in FIG. 4(c). Accordingly, it ispossible to suppress the passage of phosphorus ions through the ends ofthe floating gate and control gate electrodes 20, 22. Thus, anonvolatile semiconductor memory device including highly insulating andreliable gate oxide film 12 and interlevel dielectric film 21 can beobtained. In addition, rewriting can be performed in the nonvolatilesemiconductor memory device a far greater number of times and variousdisturb characteristics can be improved.

[0093] Moreover, the CVD insulator film 19 is grown by a CVD process ata temperature as low as about 800° C. or less. Accordingly, unlikeforming a thick protective oxide film by thermal oxidation, both ends ofthe portion of the gate oxide film 12 under the floating gate electrode20, i.e., its portion actually functioning as a gate insulator film, arenot thickened. In other words, no bird's beaks are formed at the ends.Thus, the gate length can be controlled accurately and this method isadvantageously applicable to the miniaturization of a semiconductordevice. Similarly, thickening (or formation of bird's beaks) at the endsof the ONO interlevel dielectric film 21 can also be suppressed.Accordingly, it is also possible to suppress the variation incharacteristics of the device, which is ordinarily caused because of thelocal application of stress to the ends of an interlevel dielectricfilm.

[0094] Moreover, since a CVD process is conducted at a lower temperaturethan a thermal oxidation process, it is possible to prevent the dopantssuch as phosphorus introduced into the floating gate electrode 20 fromdiffusing downward to reach the gate oxide film 12 or the Si substrate11.

[0095] Furthermore, by covering the floating gate and control gateelectrodes 20, 22 with the CVD insulator film 19, it is also possible toprevent the dopants in these electrodes 20, 22 from diffusing to reachexternal members. As a result, a nonvolatile semiconductor memory devicewith less variable characteristics can be advantageously obtained.

[0096] Also, since the floating gate electrode 20 is covered with theCVD insulator film 19 of good quality, a nonvolatile semiconductormemory device excelling in charge retention characteristics can beobtained.

[0097] It should be noted that before or after the process step ofimplanting phosphorus ions 23 shown in FIG. 4(c), B (boron) or BF₂ ionsmay be implanted through the CVD insulator film 19 and the gate oxidefilm 12 into the Si substrate 11 to form a P-type layer as a thresholdcontrolling layer or a punch through stopper. It is clear that the sameeffects as those of this embodiment can be attained even in such a case.

[0098] Embodiment 4

[0099] Next, the fourth embodiment of the present invention will bedescribed. FIGS. 5(a) through 5(c) are cross-sectional viewsillustrating respective process steps for fabricating a semiconductordevice functioning as a nonvolatile semiconductor memory device of thisembodiment.

[0100] As shown in FIG. 5(c), the device includes: an Si substrate 11; agate oxide film 12; source/drain layers 17 and 18; a CVD insulator film19; a floating gate electrode 20; an interlevel dielectric film 21; anda control gate electrode 22. The CVD insulator film 19 is made ofsilicon dioxide deposited by a CVD process. In FIG. 5(c), the referencenumeral 23 denotes phosphorus ions implanted as dopant ions into the Sisubstrate 11 to form the source/drain layers 17 and 18.

[0101] First, in the process step shown in FIG. 5(a), a gate oxide film12, made of silicon dioxide, is formed to be 9 nm thick on a P-typesilicon substrate 11. Then, a floating gate electrode 20 made ofphosphorus-doped polysilicon, an interlevel dielectric film 21 made ofONO (three-layered film in which a nitride film is sandwiched between apair of oxide films), and a control gate electrode 22 made ofphosphorus-doped polysilicon are sequentially stacked thereon.

[0102] Next, in the process step shown in FIG. 5(b), a CVD insulatorfilm 19, made of silicon dioxide, is deposited by RPCVD to be 10 nmthick over the substrate to cover the gate oxide film 12 and themultilevel structure including the floating gate electrode 20,interlevel dielectric film 21 and control gate electrode 22.Subsequently, the CVD insulator film 19 is etched anisotropically toleave its portions on the side faces of the floating gate electrode 20,interlevel dielectric film 21 and control gate electrode 22. At the sametime, the gate oxide film 12 is also etched anisotropically to leave itsportion under the floating gate electrode 20.

[0103] Then, in the process step shown in FIG. 5(c), phosphorus ions 23are implanted into the Si substrate 11 from above the CVD insulator film19, control gate electrode 22, interlevel dielectric film 21 andfloating gate electrode 20. As a result, N-type source/drain layers 17and 18 are formed in the Si substrate 11 on both sides of the floatinggate electrode 20. The implantation is performed under the conditionsthat the implant energy is 50 keV and the dose is 5×10¹⁵ cm⁻², forexample. Also, in order to prevent channeling, the ions are implanted ata tilt angle of about 7 degrees with respect to a normal of thesubstrate surface.

[0104] In accordance with the method of this embodiment, the side facesof the floating gate electrode 20 are covered with the CVD insulatorfilm 19 in the process step shown in FIG. 5(c). Accordingly, it ispossible to suppress the passage and introduction of the phosphorusions, implanted into the Si substrate 11 to form the source/drain layers17 and 18, through the ends of the floating gate electrode 20 into thegate oxide film 12. Moreover, in the process step of growing the CVDinsulator film 19, thickening, or formation of bird's beaks, involvedwith thermal oxidation, can be suppressed at both ends of the gate oxidefilm 12, as in the third embodiment. Thus, the gate length can becontrolled accurately and this method is advantageously applicable tothe miniaturization of a semiconductor device. Similarly, thickening (orformation of bird's beaks) at the ends of the ONO interlevel dielectricfilm 21 can also be suppressed. Accordingly, it is also possible tosuppress the variation in device characteristics, ordinarily resultingfrom the local application of stress to the ends of an interleveldielectric film. Thus, the same effects as those of the fourthembodiment can also be attained.

[0105] Also, if the steps of coating the gate electrodes 20, 22 with theCVD insulator film 19 and implanting the phosphorus ions are repeatedlyperformed twice or more with a gradually increased doping level, then asource/drain structure having a gentler dopant concentration profile canbe obtained. As a result, a nonvolatile semiconductor memory deviceexhibiting excellent electrical characteristics is realized.

[0106] It should be noted that before or after the step of implantingphosphorus ions 23 shown in FIG. 5(c), B (boron) or BF₂ ions may beimplanted into the Si substrate 11 from above the CVD insulator film 19and the gate oxide film 12 to form a P-type layer as a thresholdcontrolling layer or a punch through stopper. It is clear that the sameeffects as those of this embodiment can be attained even in such a case.

Appropriate Thickness Range of CVD Insulator Film

[0107] Next, an appropriate thickness range of the CVD insulator film 19defined in the third and fourth embodiments will be described.

[0108] In the third and fourth embodiments, the appropriate thicknessrange of the CVD insulator film 19 is the same as that defined in thefirst and second embodiments. As can be understood from the dependenceof leakage characteristics of the gate oxide film on the thickness ofthe CVD insulator film (see FIG. 3), if the thickness of the CVDinsulator film is 5 nm or more, then the damage caused in the gate oxidefilm due to ion implantation can be greatly reduced. The thicker the CVDinsulator film is, the more remarkably the damage can be reduced.However, in order to overlap the LDD layers with the gate electrode byan appropriate distance without conducting excessive heat treatment, thethickness of the CVD insulator film is preferably 30 nm or less.

[0109] In the third and fourth embodiments, the CVD insulator film 19 ismade of silicon dioxide. Alternatively, the CVD insulator film 19 may bemade of silicon nitride. With the silicon dioxide CVD insulator film 19,the stress applied to an underlying film can be smaller than a siliconnitride film. On the other hand, with a silicon nitride CVD insulatorfilm 19, the formation of bird's beaks in the gate oxide film 12 and theinterlevel dielectric film 21 can be advantageously suppressed moreeffectively during subsequent process steps performed at a hightemperature like diffusing the dopants. The same trade-off rule is alsotrue of the embodiments of a nonvolatile semiconductor memory device tobe described below.

[0110] Embodiment 5

[0111] Next, the fifth embodiment of the present invention will bedescribed. FIG. 6 is a cross-sectional view of a semiconductor devicefunctioning as a MOSFET of this embodiment.

[0112] As shown in FIG. 6, the device includes: a P-type Si substrate11; an SiO₂ gate oxide film 12; a polysilicon gate electrode 13; N-typeLDD layers 15 a, 15 b; TEOS sidewall spacers 16 a, 16 b; N-typesource/drain layers 17 and 18; and a CVD insulator film 19 made of SiO₂deposited by CVD.

[0113] The semiconductor device of this embodiment is characterized inthat the gate oxide film 12 is formed only under the gate electrode 13and that the sidewall spacers 16 a and 16 b are formed on the gate oxidefilm 12 and over the side faces of the gate electrode 13. Such astructure can be easily formed by patterning the gate oxide film 12 inthe same shape as that of the gate electrode 13 in the step shown inFIG. 2(a) of the second embodiment and then performing the same processsteps as those illustrated in FIGS. 2(b) through 2(e).

[0114] In this embodiment as well as in the second embodiment, it isalso possible to suppress the deterioration in insulating properties ofthe gate oxide film 12 due to the passage of dopant ions through theends of the gate electrode 13 during the implantation of dopant ions toform the LDD layers 15 a and 15 b. As a result, a semiconductor deviceincluding a highly insulating and reliable gate oxide film can beobtained. In other words, the reliability of the semiconductor devicecan be improved.

[0115] In addition, since the gate electrode 13 is covered with the CVDinsulator film 19, the diffusion of the dopants, introduced into thegate electrode 13, toward the side and upper surfaces thereof can besuppressed. Consequently, a semiconductor device with less variablecharacteristics is realized.

[0116] Embodiment 6

[0117] Next, the sixth embodiment of the present invention will bedescribed. FIG. 7 is a cross-sectional view of a semiconductor devicefunctioning as a nonvolatile semiconductor memory device of thisembodiment.

[0118] As shown in FIG. 7, the device includes: a P-type Si substrate11; an SiO₂ gate oxide film 12; N-type source/drain layers 17 and 18; aCVD insulator film 19 made of SiO₂ deposited by CVD; a polysiliconfloating gate electrode 20; an ONO interlevel dielectric film 21 (i.e.,a three-layered film in which a nitride film is sandwiched between apair of oxide films); and a polysilicon control gate electrode 22.

[0119] The device of this embodiment is characterized in that the gateoxide film 12 is formed only under the floating gate electrode 20 andthat the sidewall spacers 16 a, 16 b are formed on the gate oxide film12 and the side faces of the control gate electrode 22, interleveldielectric film 21 and floating gate electrode 20. Such a structure canbe easily formed by patterning the gate oxide film 12 in the same shapeas that of the control gate electrode 22, interlevel dielectric film 21and floating gate electrode 20 in the step shown in FIG. 5(a) of thefourth embodiment and then performing the same process steps as those inFIGS. 5(b) and 5(c).

[0120] In this embodiment as well as in the fourth embodiment, it isalso possible to suppress the deterioration in insulating properties ofthe gate oxide film 12 because of the passage of dopant ions through theends of the floating gate electrode 20 during the implantation of dopantions to form the source/drain layers 17 and 18. As a result, anonvolatile semiconductor memory device including a highly insulatingand reliable gate oxide film can be obtained. That is to say, rewritingcan be performed in the nonvolatile semiconductor memory device a fargreater number of times and various disturb characteristics can beimproved.

[0121] In addition, since the floating gate electrode 20 is covered withthe CVD insulator film 19, it is possible to prevent the dopants,introduced into the floating gate electrode 20, from diffusing towardexternal members. Consequently, a nonvolatile semiconductor memorydevice with less variable characteristics is realized.

[0122] Moreover, since the floating gate electrode 20 is covered withthe CVD insulator film 19 of good quality, a nonvolatile semiconductormemory device excelling in charge retention characteristics can beobtained.

[0123] Embodiment 7

[0124] Next, the seventh embodiment of the present invention will bedescribed. FIGS. 8(a) through 8(f) are cross-sectional viewsillustrating respective process steps for fabricating a semiconductordevice functioning as a MOSFET of this embodiment.

[0125] As shown in FIG. 8(f), the device includes: an Si substrate 11; agate oxide film 12; a gate electrode 13; LDD layers 15 a, 15 b; sidewallspacers 16 a, 16 b; source/drain layers 17 and 18; a CVD insulator film19; and a thermal oxide film 30. The CVD insulator film 19 is made ofsilicon dioxide deposited by a CVD process. In FIG. 8(c), the referencenumeral 14 denotes arsenic ions implanted as dopant ions into the Sisubstrate 11 to form the LDD layers 15 a and 15 b.

[0126] First, in the process step shown in FIG. 8(a), a gate oxide film12, made of silicon dioxide, is formed to be 9 nm thick by pyrogenicoxidation technique on a P-type silicon substrate 11. Then, a gateelectrode 13, made of phosphorus-doped polysilicon, is formed thereon.

[0127] Next, in the process step shown in FIG. 8(b), a CVD insulatorfilm 19, made of silicon dioxide, is deposited by RPCVD to be 15 nmthick over the substrate to cover the gate oxide film 12 and the gateelectrode 13.

[0128] Then, in the process step shown in FIG. 8(c), arsenic ions 14 areimplanted into the Si substrate 11 from above the gate electrode 13 andthe CVD insulator film 19 to form N-type LDD layers 15 a and 15 b in theSi substrate 11 on both sides of the gate electrode 13. The implantationis performed under the conditions that the implant energy is 50 keV andthe dose is 5×10¹⁴ cm⁻², for example. Also, in order to make the LDDlayers 15 a and 15 b extend to reach a region near the gate electrode13, the ions are implanted at a tilt angle of about 25 degrees withrespect to a normal of the substrate surface (where implantation isperformed at four steps).

[0129] Then, in the process step shown in FIG. 8(d), rapid thermalannealing is conducted within an oxygen ambient (e.g., oxidizing andnitriding ambient) at 850° C. in order to repair the damage caused inthe gate oxide film 12. As a result of this treatment, the Si substrate11 and the gate electrode 13 are thermally oxidized to form a thermaloxide film 30 to be about 5 nm thick. During this process step, the gateoxide film 12 is slightly thickened except for its portion under thegate electrode 13 (i.e., its portion actually functioning as a gateinsulator film). Also, the thickened region reaches the region under thegate electrode 13. Accordingly, small bird's beaks are formed at bothends of the portion of the gate oxide film 12 actually functioning as agate insulator film.

[0130] Subsequently, in the process step shown in FIG. 8(e), a TEOS filmis deposited over the substrate and etched anisotropically, therebyforming sidewall spacers 16 a and 16 b out of the TEOS film over theside faces of the gate electrode 13 with the CVD insulator film 19interposed therebetween. During this process step, the gate oxide film12, thermal oxide film 30 and CVD insulator film 19 on the Si substrate11 are removed.

[0131] Finally, in the process step shown in FIG. 8(f), arsenic ions areimplanted into the Si substrate 11 from above the gate electrode 13, CVDinsulator film 19, thermal oxide film 30 and sidewall spacers 16 a and16 b. As a result, N-type source/drain layers 17 and 18 are formed alongthe outer periphery of the LDD layers 15 a and 15 b. The implantation isperformed under the conditions that the implant energy is 50 keV and thedose is 2×10¹⁵ cm⁻², for example. Also, in order to prevent channeling,the ions are implanted at a tilt angle of about 7 degrees with respectto a normal of the substrate surface.

[0132] In accordance with the method of this embodiment, by covering theside faces of the gate electrode 13 with the CVD insulator film 19 inthe process step shown in FIG. 8(b), the same effects as those of thefirst embodiment can also be attained. That is to say, since the passageof arsenic ions 14 through the ends of the gate electrode 13 can besuppressed in the process step shown in FIG. 8(c), the damage caused inthe gate oxide film 12 can be reduced. Also, a long-timehigh-temperature heat treatment for forming a protective film is notperformed and the CVD insulator film 19 is provided in this embodiment.Accordingly, formation of large bird's beaks in the portion of the gateoxide film 12 functioning as a gate insulator film and the diffusion ofdopants such as phosphorus in the gate electrode 13 toward externalmembers can be suppressed.

[0133] In addition, since a heat treatment is conducted within anoxidizing ambient in the step shown in FIG. 8(d), the gate oxide film12, having received damage due to the implantation of arsenic ions 14and had the insulating properties deteriorated, can be re-oxidized torecover its insulating properties. That is to say, although the passageof arsenic ions 14 through the gate electrode 13 can be satisfactorilysuppressed in the step shown in FIG. 8(c), it is impossible to totallyeliminate the passage. If thermal oxidation is conducted in such a case,then some reparation seems to happen to repair the damage caused in thegate oxide film 12. Specifically, silicon-oxide recombination mightoccur in the regions where silicon-oxygen atomic bonds have been broken.By adding a process step like this for repairing the damage caused inthe gate oxide film 12, a semiconductor device including a more highlyreliable gate oxide film 12 than that of the first or second embodimentcan be obtained.

[0134] In this case, the thermal oxidation process illustrated in FIG.8(d) is performed only briefly just to repair the damage caused in thegate oxide film 12, unlike the process step of forming a thermal oxidefilm as a protective film. Accordingly, not so large bird's beaks areformed in the gate oxide film 12. Thus, the variation or deteriorationin characteristics of the device, which ordinarily happens in aconventional method because of a variable gate length, can be avoided.

[0135] In particular, since rapid thermal annealing is performed as aheat treatment within an oxynitriding ambient, the heat treatment can beminimized, resulting in a smaller degree of variation incharacteristics. Thus, this method is advantageously applicable to theminiaturization of a semiconductor device.

[0136] It should be noted that the heat treatment within the oxidizingambient shown in FIG. 8(d) may be performed not just for recovering theinsulation properties of the gate oxide film 12 but for annealing theLDD layers 15 a and 15 b.

[0137] Furthermore, even if phosphorus ions are implanted to increasethe breakdown voltage of the drain layer or boron or BF₂ ions areimplanted to form a punch through stopper before or after the step shownin FIG. 8(c), the same effects as those of this exemplary embodiment canbe attained.

[0138] Embodiment 8

[0139] Next, the eighth embodiment of the present invention will bedescribed. FIGS. 9(a) through 9(f) are cross-sectional viewsillustrating respective process steps for fabricating a semiconductordevice functioning as a MOSFET of this embodiment.

[0140] As shown in FIG. 9(f), the device includes: an Si substrate 11; agate oxide film 12; a gate electrode 13; LDD layers 15 a, 15 b; sidewallspacers 16 a, 16 b; source/drain layers 17, 18; a CVD insulator film 19;and an oxynitride film 31. The CVD insulator film 19 is made of silicondioxide deposited by a CVD process. In FIG. 9(c), the reference numeral14 denotes arsenic ions implanted as dopant ions into the Si substrate11 to form the LDD layers 15 a and 15 b.

[0141] First, in the process step shown in FIG. 9(a), a gate oxide film12, made of silicon dioxide, is formed to be 9 nm thick by pyrogenicoxidation technique on a P-type silicon substrate 11. Then, a gateelectrode 13, made of phosphorus-doped polysilicon, is formed thereon.

[0142] Next, in the process step shown in FIG. 9(b), a CVD insulatorfilm 19, made of silicon dioxide, is deposited by RPCVD to be 15 nmthick over the substrate to cover the gate oxide film 12 and the gateelectrode 13.

[0143] Then, in the process step shown in FIG. 9(c), arsenic ions 14 areimplanted into the Si substrate 11 from above the gate electrode 13 andthe CVD insulator film 19 to form N-type LDD layers 15 a and 15 b in theSi substrate 11 on both sides of the gate electrode 13. The implantationis performed under the conditions that the implant energy is 50 keV andthe dose is 5×10¹⁴ cm⁻², for example. Also, in order to make the LDDlayers 15 a and 15 b extend to reach a region near the gate electrode13, the ions are implanted at a tilt angle of about 25 degrees withrespect to a normal of the substrate surface (where implantation isperformed at four steps).

[0144] Subsequently, in the process step shown in FIG. 9(d), rapidthermal annealing is conducted for repairing the damage caused in thegate oxide film 12 within an N₂O ambient (i.e., oxidizing and nitridingambient) at 1000° C. As a result of this treatment, the Si substrate 11and the gate electrode 13 are oxidized and nitrided to form a very thinoxynitride film 31 to be about 3 nm thick. During this process step, thegate oxide film 12 is slightly thickened except for its portion underthe gate electrode 13 (i.e., the portion actually functioning as a gateinsulator film). Also, since the thickened region reaches the regionunder the gate electrode 13, small bird's beaks are formed at both endsof the portion of the gate oxide film 12 actually functioning as thegate insulator film.

[0145] Subsequently, in the process step shown in FIG. 9(e), a TEOS filmis deposited over the substrate and etched anisotropically, therebyforming sidewall spacers 16 a and 16 b out of the TEOS film over theside faces of the gate electrode 13 with the CVD insulator film 19interposed therebetween.

[0146] Finally, in the process step shown in FIG. 9(f), arsenic ions areimplanted into the Si substrate 11 from above the gate electrode 13, CVDinsulator film 19 and sidewall spacers 16 a and 16 b. As a result,N-type source/drain layers 17 and 18 are formed in the Si substrate 11along the outer periphery of the LDD layers 15 a and 15 b. Theimplantation is performed under the conditions that the implant energyis 50 keV and the dose is 2×10¹⁵ cm⁻², for example. Also, in order toprevent channeling, the ions are implanted at a tilt angle of about 7degrees with respect to a normal of the substrate surface.

[0147] In accordance with the method of this embodiment, by covering theside faces of the gate electrode 13 with the CVD insulator film 19 inthe step shown in FIG. 9(b), the same effects as those of the seventhembodiment can also be attained. That is to say, since the passage ofarsenic ions 14 through the ends of the gate electrode 13 can besuppressed in the step shown in FIG. 9(c), the damage caused in the gateoxide film 12 can be reduced. Also, a long-time high-temperature heattreatment for forming a protective film is not performed and the CVDinsulator film 19 is provided in this embodiment. Accordingly, formationof large bird's beaks and diffusion of dopants such as phosphorus in thegate electrode 13 toward external members can be suppressed.

[0148] In addition, since a heat treatment is conducted within anoxidizing and nitriding ambient in the step shown in FIG. 9(d), the gateoxide film 12, having received damage due to the implantation of arsenicions 14 and had the insulating properties deteriorated, can bere-oxidized to recover its insulating properties. Furthermore, since thegate oxide film 12 is also nitrided during this process step, danglingbonds existing between the Si substrate 11 and the gate oxide film 12can be repaired. Accordingly, deterioration in characteristics of thegate oxide film 12 after the application of electrical stress can bealleviated and electron trapping in the gate oxide film 12 can bereduced. As a result, a semiconductor device including a very highlyreliable gate oxide film can be obtained. In other words, thereliability of the semiconductor device can be tremendously improved.

[0149] Moreover, since rapid thermal annealing is performed as a heattreatment within an oxidizing and nitriding ambient, the heat treatmentcan be minimized, resulting in a smaller degree of variation incharacteristics. Thus, this method is advantageously applicable to theminiaturization of a semiconductor device.

[0150] Furthermore, since the oxidizing and nitriding step shown in FIG.9(d) is rapid thermal annealing, the bird's beaks formed in the gateoxide film 12, if any, are extremely small. Thus, variation ordeterioration in characteristics of the device, which ordinarily happensin a conventional method because of a variable gate length, can beavoided. And the fabrication process of this embodiment is more suitablefor the miniaturization of a MOSFET.

[0151] It should be noted that the heat treatment within the oxidizingand nitriding ambient shown in FIG. 9(d) may be performed not just forrecovering the insulation properties of the gate oxide film 12 but forannealing the LDD layers 15 a and 15 b.

[0152] Furthermore, even if phosphorus ions are implanted to increasethe breakdown voltage of the drain layer or boron or BF₂ ions areimplanted to form a punch through stopper before or after the step shownin FIG. 9(c), the same effects as those of this exemplary embodiment canbe attained.

[0153] Embodiment 9

[0154] Next, the ninth embodiment of the present invention will bedescribed. FIGS. 10(a) through 10(f) are cross-sectional viewsillustrating respective process steps for fabricating a semiconductordevice functioning as a MOSFET of this embodiment.

[0155] As shown in FIG. 10(f), the device includes: an Si substrate 11;a gate oxide film 12; a gate electrode 13; LDD layers 15 a, 15 b;sidewall spacers 16 a, 16 b; source/drain layers 17, 18; and a CVDinsulator film 19. The CVD insulator film 19 is made of silicon dioxidedeposited by a CVD process. In FIG. 10(c), the reference numeral 14denotes arsenic ions implanted as dopant ions into the Si substrate 11to form the LDD layers 15 a and 15 b.

[0156] First, in the process step shown in FIG. 10(a), a gate oxide film12, made of silicon dioxide, is formed to be 9 nm thick by pyrogenicoxidation technique on a P-type silicon substrate 11. Then, a gateelectrode 13 made of phosphorus-doped polysilicon is formed thereon.

[0157] Next, in the process step shown in FIG. 10(b), a CVD insulatorfilm 19, made of silicon dioxide, is deposited by RPCVD to be 25 nmthick over the substrate to cover the gate oxide film 12 and the gateelectrode 13.

[0158] Thereafter, in the process step shown in FIG. 10(c), arsenic ions14 are implanted into the Si substrate 11 from above the gate electrode13 and the CVD insulator film 19 to form N-type LDD layers 15 a, 15 b inthe Si substrate 11 on both sides of the gate electrode 13. Theimplantation is performed under the conditions that the implant energyis 50 keV and the dose is 5×10¹⁴ cm⁻², for example. Also, in order tomake the LDD layers 15 a and 15 b extend to reach a region near the gateelectrode 13, the ions are implanted at a tilt angle of about 25 degreeswith respect to a normal of the substrate surface (where implantation isperformed at four steps).

[0159] Subsequently, in the process step shown in FIG. 10(d), rapidthermal annealing is conducted within a nitriding ambient containing NO,NH₃ or the like at 1050° C. As a result of this treatment, both ends ofthe portion of the gate oxide film 12 under the gate electrode 13 (i.e.,its portion actually functioning as a gate insulator film) are nitrided.However, neither the oxide film 30 of the seventh embodiment nor theoxynitride film 31 of the eighth embodiment is formed. Bird's beaks arenot formed in the gate oxide film 12, either.

[0160] Subsequently, in the process step shown in FIG. 10(e), a TEOSfilm is deposited over the substrate and etched anisotropically, therebyforming sidewall spacers 16 a and 16 b over the side faces of the gateelectrode 13 with the CVD insulator film 19 interposed therebetween.

[0161] Finally, in the process step shown in FIG. 10(f), arsenic ionsare implanted into the Si substrate 11 from above the gate electrode 13,CVD insulator film 19 and sidewall spacers 16 a and 16 b. As a result,N-type source/drain layers 17 and 18 are formed along the outerperiphery of the LDD layers 15 a and 15 b. The implantation is performedunder the conditions that the implant energy is 50 keV and the dose is2×10¹⁵ cm⁻², for example. Also, in order to prevent channeling, the ionsare implanted at a tilt angle of about 7 degrees with respect to anormal of the substrate surface.

[0162] In accordance with the method of this embodiment, by covering theside faces of the gate electrode 13 with the CVD insulator film 19 inthe step shown in FIG. 10(b), the same effects as those of the seventhembodiment can also be attained. That is to say, the damage caused bythe arsenic ions 14 in the gate oxide film 12 can be reduced in the stepshown in FIG. 10(c). Also, a long-time high-temperature heat treatmentfor forming a protective film is not performed and the CVD insulatorfilm 19 is provided in this embodiment. Accordingly, formation of largebird's beaks and diffusion of dopants such as phosphorus in the gateelectrode 13 toward external members can be suppressed.

[0163] In addition, since a heat treatment is conducted within anoxidizing and nitriding ambient in the step shown in FIG. 10(d), bothends of the gate oxide film 12 are nitrided. As a result, dangling bondsexisting between the Si substrate 11 and the gate oxide film 12 can berepaired. Accordingly, deterioration in properties of the gate oxidefilm 12 after the application of electrical stress can be alleviated andelectron trapping in the gate oxide film 12 can be reduced.Consequently, a MOSFET including a very highly reliable gate oxide filmcan be obtained. In other words, the reliability of the MOSFET can betremendously improved.

[0164] Moreover, since rapid thermal annealing is performed as a heattreatment within an oxidizing and nitriding ambient, the heat treatmentcan be minimized, resulting in a smaller degree of variation incharacteristics of the MOSFET. Thus, this method is advantageouslyapplicable to the miniaturization of a MOSFET.

[0165] Furthermore, in the process step illustrated in FIG. 10(d) usinga nitride, no bird's beaks are formed in the gate oxide film 12. Thus,variation or deterioration in characteristics of the device, whichordinarily happens in a conventional method because of a variable gatelength, can be avoided. And the fabrication process of this embodimentis more suitable for the miniaturization of a MOSFET.

[0166] It should be noted that the heat treatment within the oxidizingand nitriding ambient shown in FIG. 10(d) may also be performed forannealing the LDD layers 15 a and 15 b.

[0167] Furthermore, even if phosphorus ions are implanted to increasethe breakdown voltage of the drain layer or boron or BF₂ ions areimplanted to form a punch through stopper before or after the step shownin FIG. 10(c), the same effects as those of this exemplary embodimentcan be attained.

[0168] Embodiment 10

[0169] Next, the tenth embodiment of the present invention will bedescribed. FIGS. 11(a) through 11(d) are cross-sectional viewsillustrating respective process steps for fabricating a semiconductordevice functioning as a nonvolatile semiconductor memory device of thisembodiment.

[0170] As shown in FIG. 11(d), the device includes: an Si substrate 11;a gate oxide film 12; source/drain layers 17, 18; an insulator film 19deposited by CVD; a floating gate electrode 20; an interlevel dielectricfilm 21; a control gate electrode 22; and a thermal oxide film 30. InFIG. 4(c), the reference numeral 23 denotes phosphorus ions implanted asdopant ions into the Si substrate 11 to form the source/drain layers 17and 18.

[0171] First, in the process step shown in FIG. 11(a), a gate oxide film12, made of silicon dioxide, is formed to be 9 nm thick by a pyrogenicoxidation technique on a P-type silicon substrate 11. Then, a floatinggate electrode 20 made of phosphorus-doped polysilicon, an ONOinterlevel dielectric film 21 (three-layered film in which a nitridefilm is sandwiched between a pair of oxide films) and a control gateelectrode 22 made of phosphorus-doped polysilicon are sequentiallystacked thereon.

[0172] Next, in the process step shown in FIG. 11(b), a CVD insulatorfilm 19, made of silicon dioxide, is deposited by RPCVD to be 20 nmthick over the substrate to cover the gate oxide film 12 and themultilevel structure including the floating gate electrode 20,interlevel dielectric film 21 and control gate electrode 22.

[0173] Subsequently, in the process step shown in FIG. 11(c), phosphorusions 23 are implanted into the Si substrate 11 from above the controlgate electrode 22, interlevel dielectric film 21 and floating gateelectrode 20 covered with the CVD insulator film 19 to form N-typesource/drain layers 17, 18 in the Si substrate 11 on both sides of thefloating gate electrode 20. The implantation is performed under theconditions that the implant energy is 70 keV and the dose is 5×10¹⁵cm⁻², for example. Also, in order to prevent channeling, the ions areimplanted at a tilt angle of about 7 degrees with respect to a normal ofthe substrate surface.

[0174] Then, in the process step shown in FIG. 11(d), a heat treatmentis conducted within an oxygen ambient at 850° C. to repair the damagecaused in the gate oxide film 12. As a result of this treatment, the Sisubstrate 11, control gate electrode 22 and floating gate electrode 20are thermally oxidized to form a thermal oxide film 30 to be about 8 nmthick. During this process step, the gate oxide film 12 is slightlythickened except for its portion under the floating gate electrode 20(i.e., its portion actually functioning as a gate insulator film). Also,since the thickened region reaches the region under the floating gateelectrode 20, small bird's beaks are formed at both ends of the portionof the gate oxide film 12 actually functioning as a gate insulator film.Similarly, both ends of the oxide films sandwiching the nitride film inthe interlevel dielectric film 21 are also slightly thickened to formsmall bird's beaks in the interlevel dielectric film 21.

[0175] In accordance with the method of this embodiment, the side facesof the control gate and floating gate electrodes 22, 20 are covered withthe CVD insulator film 19 in the step shown in FIG. 11(b). Thus, thesame effects as those of the third embodiment can be attained. That isto say, it is possible to suppress the passage of arsenic ions 14through the ends of the floating gate and control gate electrodes 20, 22in the step shown in FIG. 11(c). As a result, the damage caused in thegate oxide film 12 and the interlevel dielectric film 21 can be reduced.Also, a long-time high-temperature heat treatment for forming aprotective film is not performed and the CVD insulator film 19 isprovided in this embodiment. Accordingly, formation of large bird'sbeaks and diffusion of dopants such as phosphorus in the gate electrodes22, 20 toward external members can be suppressed.

[0176] In addition, since a heat treatment is conducted within anoxidizing ambient in the step shown in FIG. 11(d), the gate oxide film12 and the interlevel dielectric film 21, having received damage due tothe implantation of arsenic ions 14 and had the insulating propertiesdeteriorated, can be re-oxidized to recover their insulating properties.That is to say, although the passage of arsenic ions 14 through therespective gate electrodes 22, 20 can be considerably suppressed in thestep shown in FIG. 11(c), it is impossible to totally eliminate thepassage. If thermal oxidation is conducted in such a case, then somereparation seems to happen to repair the damage caused in the gate oxidefilm 12 and the interlevel dielectric film 21. Specifically,silicon-oxide recombination might occur in the regions wheresilicon-oxygen atomic bonds have been broken. By adding a process steplike this for repairing the damage caused in the gate oxide film 12through thermal oxidation, rewriting can be performed in the nonvolatilesemiconductor memory device a far greater number of times and variousdisturb characteristics can be improved.

[0177] In this case, the thermal oxidation process illustrated in FIG.11(d) is performed just to repair the damage caused in the gate oxidefilm 12 and the interlevel dielectric film 21, unlike a process step offorming a thermal oxide film as a protective film. Accordingly, not solarge bird's beaks are formed in the gate oxide film 12 and theinterlevel dielectric film 21. Thus, it is possible to reduce thevariation in threshold voltage resulting from a variable gate length ina conventional method. And it is also possible to suppress the variationin characteristics of the device, which is ordinarily caused due to thelocal application of stress to both ends of the interlevel dielectricfilm 21.

[0178] In particular, since rapid thermal annealing is performed as aheat treatment within an oxidizing ambient, the heat treatment can beminimized, resulting in a smaller degree of variation in characteristicsof the nonvolatile semiconductor memory device. This method is alsoapplicable to miniaturization of a nonvolatile semiconductor memorydevice.

[0179] Moreover, since the floating gate electrode 20 is covered withthe CVD insulator film 19 of good quality, a nonvolatile semiconductormemory device excelling in charge retention characteristics can beobtained.

[0180] It should be noted that before or after the step of implantingphosphorus ions 23 shown in FIG. 11(c), arsenic ions may be implantedinto the Si substrate 11 to increase a concentration at the surface andthereby facilitate the extraction of electrons. Alternatively, B (boron)or BF₂ ions may also be implanted through the CVD insulator film 19 andthe gate oxide film 12 into the Si substrate 11 to form a P-type layeras a threshold controlling layer or a punch through stopper. It is clearthat the same effects as those of this embodiment can be attained evenin those cases.

[0181]FIG. 14 is a graph illustrating in comparison data about themaximum numbers of times rewriting can be performed in respectivenonvolatile semiconductor memory devices fabricated by the methods ofthe third and tenth embodiments. In FIG. 14, the axis of abscissasindicates the maximum number of times rewriting is performed, while theaxis of ordinates indicates the threshold voltage (V). Vt1 indicatesthreshold voltages where electrons are injected into the floating gateelectrode 20, while Vt0 indicates threshold voltages where electrons areejected out of the floating gate electrode 20. The threshold voltages ofa nonvolatile semiconductor memory device fabricated by the method ofthe third embodiment are identified with X, while the threshold voltagesof a nonvolatile semiconductor memory device fabricated by the method ofthe tenth embodiment are identified with . We confirmed that thethreshold voltage of the nonvolatile semiconductor memory devicefabricated by the method of the third embodiment is less variable thanthe threshold voltage (not shown) of a nonvolatile semiconductor memorydevice fabricated by the conventional method. It was also confirmed thatthe threshold voltage increases in device of the third embodiment lessthan the conventional device while electrons are being ejected. As shownin FIG. 14, the increase in threshold voltage is very small in thenonvolatile semiconductor memory device fabricated by the method of thetenth embodiment during the ejection of electrons. Thus, according tothe method of this embodiment, rewriting can be performed a considerablylarger number of times and various disturb characteristics can betremendously improved in the nonvolatile semiconductor memory device.

[0182] Embodiment 11

[0183] Next, the eleventh embodiment of the present invention will bedescribed. FIGS. 12(a) through 12(d) are cross-sectional viewsillustrating respective process steps for fabricating a semiconductordevice functioning as a nonvolatile semiconductor memory device of thisembodiment.

[0184] As shown in FIG. 12(d), the device includes: an Si substrate 11;a gate oxide film 12; source/drain layers 17, 18; an insulator film 19deposited by CVD; a floating gate electrode 20; an interlevel dielectricfilm 21; a control gate electrode 22; and an oxynitride film 31. In FIG.12(c), the reference numeral 23 denotes phosphorus ions implanted asdopant ions into the Si substrate 11 to form the source/drain layers 17and 18.

[0185] First, in the process step shown in FIG. 12(a), a gate oxide film12, made of silicon dioxide, is formed to be 9 nm thick by a pyrogenicoxidation technique on a P-type silicon substrate 11. Then, a floatinggate electrode 20 made of phosphorus-doped polysilicon, an ONOinterlevel dielectric film 21 (three-layered film in which a nitridefilm is sandwiched between a pair of oxide films) and a control gateelectrode 22 made of phosphorus-doped polysilicon are sequentiallystacked thereon.

[0186] Next, in the process step shown in FIG. 12(b), a CVD insulatorfilm 19, made of silicon dioxide, is deposited by RPCVD to be 20 nmthick over the substrate to cover the gate oxide film 12 and themultilevel structure including floating gate electrode 20, interleveldielectric film 21 and control gate electrode 22.

[0187] Subsequently, in the process step shown in FIG. 12(c), phosphorusions 23 are implanted into the Si substrate 11 from above the controlgate electrode 22, interlevel dielectric film 21 and floating gateelectrode 20 covered with the CVD insulator film 19. As a result, N-typesource/drain layers 17 and 18 are formed in the Si substrate 11 on bothsides of the floating gate electrode 20. The implantation is performedunder the conditions that the implant energy is 70 keV and the dose is5×10¹⁵ cm⁻², for example. Also, in order to prevent channeling, the ionsare implanted at a tilt angle of about 7 degrees with respect to anormal of the substrate surface.

[0188] Then, in the process step shown in FIG. 12(d), a heat treatmentis conducted within an oxidizing and nitriding ambient containing N₂O at1000° C. to repair the damage caused in the gate oxide film 12. As aresult of this treatment, the Si substrate 11, control gate electrode 22and floating gate electrode 20 are oxidized and nitrided to form anoxynitride film 31 to be about 3 nm thick. During this process step, thegate oxide film 12 is slightly thickened except for its portion underthe floating gate electrode 20 (i.e., its portion actually functioningas a gate insulator film). Also, the thickened region reaches the regionunder the floating gate electrode 20. Accordingly, very small bird'sbeaks are formed at both ends of the portion of the gate oxide film 12actually functioning as a gate insulator film. Similarly, both ends ofthe oxide films sandwiching the nitride film in the interleveldielectric film 21 are also slightly thickened to form very small bird'sbeaks in the interlevel dielectric film 21.

[0189] In accordance with the method of this embodiment, the side facesof the control gate and floating gate electrodes 22, 20 are covered withthe CVD insulator film 19 in the step shown in FIG. 12(b). Thus, thesame effects as those of the tenth embodiment can be attained. That isto say, it is possible to suppress the passage of arsenic ions 14through the floating gate and control gate electrodes 20, 22 in the stepshown in FIG. 12(c). As a result, the damage caused in the gate oxidefilm 12 and the interlevel dielectric film 21 can be reduced. Also, along-time high-temperature heat treatment for forming a protective filmis not performed and the CVD insulator film 19 is provided in thisembodiment. Accordingly, formation of large bird's beaks and diffusionof dopants such as phosphorus in the gate electrodes 22, 20 towardexternal members can be suppressed.

[0190] In addition, since a heat treatment is conducted within anoxidizing and nitriding ambient in the step shown in FIG. 12(d), thegate oxide film 12, having received damage due to the implantation ofphosphorus ions 23 and had the insulating properties deteriorated, canbe re-oxidized to recover its insulating properties. At the same time,by nitriding the gate oxide film 12, deterioration in characteristicsafter the application of electrical stress can be alleviated andelectron trapping can be reduced. As a result, a nonvolatilesemiconductor memory device including a very highly reliable gate oxidefilm can be obtained. In other words, rewriting can be performed in thenonvolatile semiconductor memory device a far greater number of timesand various disturb characteristics can be improved.

[0191] In this case, the oxidizing and nitriding process stepillustrated in FIG. 12(d) is performed just to repair the damage causedin the gate oxide film 12 and the interlevel dielectric film 21, unlikea process step of forming a thermal oxide film as a protective film. Andthe oxidation action of the oxidizing and nitriding process stepinfluences less than the thermal oxidation process of the tenthembodiment. Accordingly, only very small bird's beaks are formed in thegate oxide film 12 and the interlevel dielectric film 21 during thisprocess step. Thus, it is possible to reduce the variation in thresholdvoltage resulting from a variable gate length in a conventional method.And it is also possible to suppress the variation in characteristics ofthe device, which is ordinarily caused due to the local application ofstress to both ends of the interlevel dielectric film 21.

[0192] In particular, since rapid thermal annealing is performed as aheat treatment within an oxidizing and nitriding ambient, the heattreatment can be minimized, resulting in a smaller degree of variationin characteristics of the nonvolatile semiconductor memory device. Also,this method is advantageously applicable to the miniaturization of anonvolatile semiconductor memory device.

[0193] Moreover, since the floating gate electrode 20 is covered withthe CVD insulator film 19 of good quality, a nonvolatile semiconductormemory device excelling in charge retention characteristics can beobtained.

[0194] Furthermore, by covering the floating gate electrode 20 and theinterlevel dielectric film 21 with the CVD insulator film 19, it is alsopossible to prevent phosphorus ions, doped into the floating gateelectrode 20, from diffusing to reach external members. As a result, anonvolatile semiconductor memory device with less variablecharacteristics can be advantageously obtained.

[0195] It should be noted that before or after the process step ofimplanting phosphorus ions 23 shown in FIG. 12(c), arsenic ions may beimplanted into the Si substrate 11 to increase a concentration at thesurface and thereby facilitate the extraction of electrons.Alternatively, B (boron) or BF₂ ions may also be implanted through theCVD insulator film 19 and the gate oxide film 12 into the Si substrate11 to form a P-type layer as a threshold controlling layer or a punchthrough stopper. It is clear that the same effects as those of thisembodiment can be attained even in those cases.

[0196] In this embodiment, the process step of implanting phosphorusions 23 is performed to form the source/drain layers 17 and 18. Evenwhen arsenic ions are implanted before or after this process step, thesame effects as those of this embodiment can be naturally attained.

[0197] Embodiment 12

[0198] Next, the twelfth embodiment of the present invention will bedescribed. FIGS. 13(a) through 13(d) are cross-sectional viewsillustrating respective process steps for fabricating a semiconductordevice functioning as a nonvolatile semiconductor memory device of thisembodiment.

[0199] As shown in FIG. 13(d), the device includes: an Si substrate 11;a gate oxide film 12; source/drain layers 17, 18; an insulator film 19deposited by CVD; a floating gate electrode 20; an interlevel dielectricfilm 21; and a control gate electrode 22. In FIG. 13(c), the referencenumeral 23 denotes phosphorus ions implanted as dopant ions into the Sisubstrate 11 to form the source/drain layers 17 and 18.

[0200] First, in the process step shown in FIG. 13(a), a gate oxide film12, made of silicon dioxide, is formed to be 9 nm thick by a pyrogenicoxidation technique on a P-type silicon substrate 11. Then, a floatinggate electrode 20 made of phosphorus-doped polysilicon, an ONOinterlevel dielectric film 21 (three-layered film in which a nitridefilm is sandwiched between a pair of oxide films) and a control gateelectrode 22 made of phosphorus-doped polysilicon are sequentiallystacked thereon.

[0201] Next, in the process step shown in FIG. 13(b), a CVD insulatorfilm 19, made of silicon dioxide, is deposited by RPCVD to be 30 nmthick over the substrate to cover the gate oxide film 12 and themultilevel structure including floating gate electrode 20, interleveldielectric film 21 and control gate electrode 22.

[0202] Subsequently, in the process step shown in FIG. 13(c), phosphorusions 23 are implanted into the Si substrate 11 to from above the controlgate electrode 22, interlevel dielectric film 21 and floating gateelectrode 20 covered with the CVD insulator film 19 to form N-typesource/drain layers 17, 18 in the Si substrate 11 on both sides of thefloating gate electrode 20. The implantation is performed under theconditions that the implant energy is 70 keV and the dose is 5×10¹⁵cm⁻², for example. Also, in order to prevent channeling, the ions areimplanted at a tilt angle of about 7 degrees with respect to a normal ofthe substrate surface.

[0203] Then, in the process step shown in FIG. 13(d), rapid thermalannealing is conducted within a nitriding ambient containing NO, NH₃ orthe like at 1050° C. As a result of this treatment, neither the thermaloxide film 30 of the tenth embodiment nor the oxynitride film 31 of theeleventh embodiment is formed. Bird's beaks are not formed in the gateoxide film 12 or the interlevel dielectric film 21, either.

[0204] In accordance with the method of this embodiment, the side facesof the control gate electrode 22 and the floating gate electrode 20 arecovered with the CVD insulator film 19 in the step shown in FIG. 13(b).Thus, the same effects as those of the tenth embodiment can be attained.That is to say, it is possible to suppress the passage of arsenic ions14 through the floating gate and control gate electrodes 20, 22 in thestep shown in FIG. 13(c). Thus, the damage caused in the gate oxide film12 and the interlevel dielectric film 21 can be reduced. Also, along-time high-temperature heat treatment for forming a protective filmis not performed and the CVD insulator film 19 is provided in thisembodiment. Accordingly, formation of bird's beaks and diffusion ofdopants such as phosphorus in the gate electrodes 22, 20 toward externalmembers can be suppressed.

[0205] In addition, since a heat treatment is conducted within anitriding ambient in the process step shown in FIG. 13(d) to nitride thegate oxide film 12, deterioration in characteristics after theapplication of electrical stress can be alleviated and electron trappingcan be reduced. As a result, a nonvolatile semiconductor memory deviceincluding a very highly reliable gate oxide film 12 can be obtained. Inother words, rewriting can be performed in the nonvolatile semiconductormemory device a far greater number of times and various disturbcharacteristics can be improved.

[0206] In addition, no bird's beaks are formed in the gate oxide film 12and the interlevel dielectric film 21 during the nitride process shownin FIG. 13(d). Accordingly, it is possible to reduce the variation inthreshold voltage resulting from a variable gate length in aconventional method. And it is also possible to suppress the variationin characteristics of the device, which is ordinarily caused due to thelocal application of stress to both ends of the interlevel dielectricfilm 21.

[0207] In particular, since rapid thermal annealing is performed as aheat treatment within a nitriding ambient, the heat treatment can beminimized, resulting in a smaller degree of variation in characteristicsof the nonvolatile semiconductor memory device. Also, this method isadvantageously applicable to the miniaturization of a nonvolatilesemiconductor memory device.

[0208] Moreover, since the floating gate electrode 20 is covered withthe CVD insulator film 19 of good quality, a nonvolatile semiconductormemory device excelling in charge retention characteristics can beobtained.

[0209] Furthermore, by covering the floating gate electrode 20 and theinterlevel dielectric film 21 with the CVD insulator film 19, it is alsopossible to prevent phosphorus ions introduced into the floating gateelectrode 20 from diffusing to reach external members. As a result, anonvolatile semiconductor memory device with less variablecharacteristics can be advantageously obtained.

[0210] It should be noted that before or after the step of implantingphosphorus ions 23 shown in FIG. 13(c), arsenic ions may be implantedinto the Si substrate 11 to increase a concentration at the surface andthereby facilitate the extraction of electrons. Alternatively, B (boron)or BF₂ ions may also be implanted through the CVD insulator film 19 andthe gate oxide film 12 into the Si substrate 11 to form a P-type layeras a threshold controlling layer or a punch through stopper. It is clearthat the same effects as those of this embodiment can be attained evenin those cases.

Conditions of Heat Treatment

[0211] Rapid thermal annealing as the oxidizing, oxidizing/nitriding andnitriding processes in the seventh to twelfth embodiments is preferablyconducted in the range from 800° C. to 1100° C. to attain the expectedeffects like damage repair while suppressing deterioration incharacteristics of the device due to the diffusion of dopants. Also, inorder to prevent the formation of bird's beaks, the heat treatment ispreferably conducted for as short as 120 seconds or less.

[0212] In the foregoing seventh to twelfth embodiments, a protectiveoxide film may be provided instead of the CVD insulator film 19. Inthese embodiments, a thermal oxidation or oxidizing/nitriding process isperformed as a subsequent process step to repair the damage.Accordingly, even if the thickness of a protective oxide film formed bythe initial thermal oxidation is small, the diffusion of dopants stillcan be prevented without fail, because a new oxide film 30 or oxynitridefilm 31 is formed in the thermal oxidation or oxidizing/nitridingprocess. Accordingly, the formation of bird's beaks at both ends of thegate oxide film 12 and the interlevel dielectric film 21 can beminimized.

What is claimed is:
 1. A method for fabricating a semiconductor devicefunctioning as an MOS field effect transistor, the method comprising thesteps of: a) forming a gate insulator film and a gate electrode on asemiconductor substrate in this order; b) forming a CVD insulator filmto cover an exposed surface of the gate electrode by performing a CVDprocess; c) forming LDD layers in the semiconductor substrate byimplanting dopant ions into the semiconductor substrate from above thegate electrode and the CVD insulator film; d) forming sidewall spacersover the side faces of the gate electrode with the CVD insulator filminterposed therebetween; and e) forming source/drain layers in thesemiconductor substrate.
 2. The method of claim 1 , further comprising,between the steps b) and c), the step of etching anisotropically the CVDinsulator film to leave the CVD insulator film at least on the sidefaces of the gate electrode.
 3. The method of claim 1 , wherein thethickness of the CVD insulator film is in the range from 5 nm to 30 nm.4. The method of claim 1 , further comprising, posterior to the step c),the step of conducting a heat treatment within an ambient containing atleast oxygen to repair damage caused in the gate insulator film due tothe implantation of the dopant ions.
 5. The method of claim 4 , whereinthe step of conducting a heat treatment is performed within an oxidizingand nitriding ambient.
 6. A method for fabricating a semiconductordevice functioning as an MOS field effect transistor, the methodcomprising the steps of: a) forming a gate insulator film and a gateelectrode on a semiconductor substrate in this order; b) forming aninsulating coating to cover an exposed surface of the gate electrode; c)forming LDD layers in the semiconductor substrate by implanting dopantions into the semiconductor substrate from above the gate electrode andthe insulating coating; d) conducting a heat treatment within an ambientcontaining at least oxygen to repair damage caused in the gate insulatorfilm due to the implantation of the dopant ions; e) forming sidewallspacers over the side faces of the gate electrode with the insulatingcoating interposed there-between; and f) forming source/drain layers inthe semiconductor substrate.
 7. The method of claim 6 , wherein the stepd) is performed within an oxidizing and nitriding ambient.
 8. The methodof claim 6 , wherein in the step d), the heat treatment is conducted asrapid thermal annealing at a temperature in the range from 800° C. to1100° C. within 120 seconds.
 9. A method for fabricating a semiconductordevice functioning as a nonvolatile semiconductor memory device, themethod comprising the steps of: a) forming a gate insulator film, afloating gate electrode, an interlevel dielectric film and a controlgate electrode on a semiconductor substrate in this order; b) forming aCVD insulator film to cover the surfaces of the floating gate electrode,the interlevel dielectric film and the control gate electrode byperforming a CVD process; and c) forming source/drain layers in thesemiconductor substrate by implanting dopant ions into the semiconductorsubstrate from above the CVD insulator film, the control gate electrode,the interlevel dielectric film and the floating gate electrode.
 10. Themethod of claim 9 , further comprising, between the steps b) and c), thestep of etching anisotropically the CVD insulator film to leave the CVDinsulator film at least on the side faces of the floating gateelectrode.
 11. The method of claim 9 , wherein the thickness of the CVDinsulator film is in the range from 5 nm to 30 nm.
 12. The method ofclaim 9 , further comprising, posterior to the step c), the step ofconducting a heat treatment within an ambient containing at least oxygento repair damage caused in the gate insulator film due to theimplantation of the dopant ions.
 13. The method of claim 12 , whereinthe step of conducting a heat treatment is performed within an oxidizingand nitriding ambient.
 14. A method for fabricating a semiconductordevice functioning as a nonvolatile semiconductor memory device, themethod comprising the steps of: a) forming a gate insulator film, afloating gate electrode, an interlevel dielectric film and a controlgate electrode on a semiconductor substrate in this order; b) forming aninsulating coating to cover the surfaces of the floating gate electrode,the interlevel dielectric film and the control gate electrode; c)forming source/drain layers in the semiconductor substrate by implantingdopant ions into the semiconductor substrate from above the insulatingcoating, the control gate electrode, the interlevel dielectric film andthe floating gate electrode; and d) conducting a heat treatment withinan ambient containing at least oxygen to repair damage caused in thegate insulator film due to the implantation of the dopant ions.
 15. Themethod of claim 14 , wherein the step d) is performed within anoxidizing and nitriding ambient.
 16. The method of claim 14 , wherein inthe step d), the heat treatment is conducted as rapid thermal annealingat a temperature in the range from 800° C. to 1100° C. within 120seconds.